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74AC14 * 74ACT14 Hex Inverter with Schmitt Trigger Input
November 1988 Revised February 2005
74AC14 * 74ACT14 Hex Inverter with Schmitt Trigger Input
General Description
The 74AC14 and 74ACT14 contain six inverter gates each with a Schmitt trigger input. They are capable of transforming slowly changing input signals into sharply defined, jitterfree output signals. In addition, they have a greater noise margin than conventional inverters. The 74AC14 and 74ACT14 have hysteresis between the positive-going and negative-going input thresholds (typically 1.0V) which is determined internally by transistor ratios and is essentially insensitive to temperature and supply voltage variations.
Features
s ICC reduced by 50% s Outputs source/sink 24 mA s 74ACT14 has TTL-compatible inputs
Ordering Code:
Order Number 74AC14SC 74AC14SCX_NL (Note 1) 74AC14SJ 74AC14MTC 74AC14MTCX_NL (Note 1) 74AC14PC 74ACT14SC 74ACT14MTC 74ACT14MTCX_NL (Note 1) 74ACT14PC Package Number M14A M14A M14D MTC14 MTC14 N14A M14A MTC14 MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS009917
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74AC14 * 74ACT14
Logic Symbol
IEEE/IEC
Connection Diagram
Function Table Pin Descriptions
Pin Names In On Description Inputs Outputs Input A L H Output O H L
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74AC14 * 74ACT14
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI
0.5V to 7.0V 20 mA 20 mA 0.5V to VCC 0.5V 20 mA 20 mA 0.5V to VCC 0.5V r50 mA r50 mA 65qC to 150qC
140qC
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
0.5V VCC 0.5V
DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO
0.5V VCC 0.5V
40qC to 85qC
DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol VOH Parameter Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 5) Maximum Input Leakage Current Vt Maximum Positive Threshold Vt Minimum Negative Threshold VH(MAX) Maximum Hysteresis 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VH(MIN) Minimum Hysteresis 3.0 4.5 5.5 IOLD IOHD ICC (Note 5) Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current 5.5 5.5 5.5 2.0 0.002 0.001 0.001 TA Typ 2.99 4.49 5.49 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36
25qC
TA
40qC to 85qC
2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44
Units IOUT V IOH V IOH IOH IOUT V IOL V IOL 12 12
Conditions
Guaranteed Limits
50 PA
24 mA 24 mA (Note 3) 50 PA
IOL 24 mA 24 mA (Note 3) VCC, GND Worst Case VI TA
r0.1
2.2 3.2 3.9 0.5 0.9 1.1 1.2 1.4 1.6 0.3 0.4 0.5
r1.0
2.2 3.2 3.9 0.5 0.9 1.1 1.2 1.4 1.6 0.3 0.4 0.5 75
PA
V
TA V TA V TA V mA mA
Worst Case
Worst Case
Worst Case
VOLD VOHD VIN or GND
1.65V Max 3.85V Min VCC
75
20.0
PA
Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC14 * 74ACT14
AC Electrical Characteristics for AC
VCC Symbol Parameter (V) (Note 6) tPLH tPHL Propagation Delay Propagation Delay 3.3 5.0 3.3 5.0
Note 6: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V
TA CL Min 1.5 1.5 1.5 1.5
25qC
50 pF Typ 9.5 7.0 7.5 6.0 Max 13.5 10.0 11.5 8.5
TA
40qC to 85qC
CL 50 pF Max 15.0 11.0 13.0 9.5 ns ns Units
Min 1.5 1.5 1.5 1.5
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Output Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN VH(MAX) VH(MIN) Vt Vt ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum Hysteresis Minimum Hysteresis Maximum Positive Threshold Minimum Negative Threshold Maximum ICC/Input Minimum Dynamic Output Current (Note 8) Maximum Quiescent Supply Current
Note 7: All outputs loaded; thresholds on input associated with output under test. Note 8: Maximum test duration 2.0 ms, one output loaded at a time.
TA Typ 1.5 1.5 1.5 1.5 4.49 5.49
25qC
2.0 2.0 0.8 0.8 434 5.4 3.86 4.86
TA
40qC to 85qC
2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44
Guaranteed Limits
Units V V V VOUT VOUT IOUT VIN V IOH IOH V IOUT VIN
Conditions 0.1V 0.1V
or VCC 0.1V or VCC 0.1V
50PA
VIL or VIH
24 mA 24 mA (Note 7)
50 PA VIL or VIH 24 mA 24 mA (Note 7) VCC, GND Worst Case Worst Case Worst Case Worst Case VCC 2.1V 1.65V Max 3.85V Min VCC
0.001 0.001
0.1 0.1 0.36 0.36
V
IOL IOL VI TA TA TA TA VI
5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 5.5 5.5 5.5 5.5 0.6
r0.1
1.4 1.6 0.4 0.5 2.0 2.0 0.8 0.8
r1.0
1.4 1.6 0.4 0.5 2.0 2.0 0.8 0.8 1.5 75
PA
V V V V mA mA mA
VOLD VOHD VIN or GND
75
2.0 20.0
PA
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74AC14 * 74ACT14
AC Electrical Characteristics for ACT
VCC Symbol Parameter (V) (Note 9) tPLH tPHL Propagation Delay Data to Output Propagation Delay Data to Output
Note 9: Voltage Range 5.0 is 5.0V r 0.5V
TA CL Min 3.0 3.0
25qC
50 pF Typ 8.0 8.0 Max 10.0 10.0
TA
40qC to 85qC
CL Min 3.0 3.0 50 pF Max 11.0 11.0 ns ns Units
5.0 5.0
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance for AC for ACT Typ 4.5 25.0 80 Units pF pF VCC VCC OPEN 5.0V Conditions
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74AC14 * 74ACT14
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
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74AC14 * 74ACT14
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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74AC14 * 74ACT14
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
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74AC14 * 74ACT14 Hex Inverter with Schmitt Trigger Input
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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